In development of a semiconductor device, particularly a semiconductor memory device, ever finer patterning is developed for memory cells to achieve larger capacities and lower costs. For example, in a floating gate structure mounted semiconductor memory device such as a NAND nonvolatile semiconductor memory device, the wire pitch between bit lines (BL) formed in an upper portion of memory cells is made ever finer. Such finer patterning of LSIs is actively promoted to achieve performance improvement such as a faster operation and lower power consumption of elements due to higher integration and the reduction in manufacturing costs. In recent years, flash memories in minimum processing dimensions of, for example, 20 nm or so have been in mass production and still finer patterning and increasing technical difficulty are expected in the future.
A NAND nonvolatile semiconductor memory device capable of electrically rewriting data stores data by changing the amount of charges of a floating gate of a cell transistor to change a threshold voltage thereof. In general, electrons are discharged and injected between a floating gate and a semiconductor substrate via a gate dielectric film. Accordingly, the amount of charges of the floating gate is controlled. However, accompanying demands of finer patterning in recent years, various problems arise with increasingly finer patterning of circuits.
With finer patterning of NAND nonvolatile semiconductor memory devices, writing or reading performance deteriorates due to an RC delay of bit lines. As a countermeasure, a method of reducing an inter-wire capacity by forming an air gap between BLs is proposed. This is, for example, a method by which after bit lines are periodically formed, an upper portion thereof is covered with a dielectric film such that an air gap is formed between bit lines. According to such a method, the amount of dielectric film entering a space between bit lines is large and the volume ratio of air gaps formed between bit lines falls. Such a state cannot be considered to be enough to reduce the inter-wire capacity for finer patterning of circuits. For further performance improvements, the volume ratio of air gaps between bit lines needs to be increased. In such a case, however, a problem of a collapse of bit lines or the like is posed. Therefore, when the volume ratio of air gaps is increased, it is necessary to consider how to control such a problem.